2 - Technologies

In practice, a technology process flow should be built up connecting the individual process steps in series. The optimum technology is the one that minimizes the number of processing steps, while at the same time guaranteeing a specified device performance. In icrosensor structures, metal-oxide-silicon-based field-effect transistors, the so-called "MOSFET" devices are of great importance. The application of individual technology steps in an integrated processing is illustrated through the example of conventional omplementary MOS, the CMOS technology, which is often used in microsensor fabrication. In this case, both p-channel (PMOS) and n-channel (NMOS) transistors are realized on the same substrate It should be stressed that the very large scale integrated circuits need ore sophisticated and much more complicated processes at present time, however, the given example is a good demonstration for integrated processing, although the aluminum-gate processing has already been replaced by polysilicon gate technology.

Advantages

• batch production of low-cost, uniform elements,
• miniaturized elements with low power consumption,
• integration realizable in all directions,
• integration possibility of micromechanical elements.

Disdvantages

• strong temperature dependence of many electrical parameters,
• sophisticated high,
• cost processing, available only for high batch numbers,
• a number of sensor materials can not be applied on silicon surfaces,
• the sophisticated packaging technologies that often prevent exploiting the advantages of low-cost device production.

A fundamental process for the production of microstructures in sensors is the anisotropic etching of silicon. Certain chemical etchants (such as KOH, hydrazine, etc.) attack the (100) and (110) planes of silicon much faster than the (111) planes. This fact is used to produce a number of accurately defined shapes in a silicon wafer with (100) surface orientation. Typically, the wafer is first oxidized, and then this oxide is patterned using photolithography. When such a wafer is immersed into an anisotropic etchant, silicon will be removed only from the areas where no oxide is present. The etching proceeds downward in the [111] direction very rapidly, but when (111) planes are encountered, the etching effectively stops. In a (100) wafer, the (111) planes are oriented at an angle of 54.7° with respect to the surface. Thus "V" shaped grooves and, when an internal etch-stop layer (e.g., a strongly doped p+ epitaxial layer within an n-type wafer) is applied, specially shaped cavities can be precisely formed into the wafers.